BICMOS circuits are constructed by including bipolar transistors and complementary metal-oxide-semiconductor (CMOS) transistors on the same integrated circuit. Bipolar transistors are often used as output devices in BICMOS circuits to provide high output current, while CMOS transistors are used in the logic elements because of their low power operation. Therefore, a BICMOS logic circuit can operate at high speed without consuming a large amount of power.
FIG. 1 illustrates in partial schematic form and partial logic diagram form a prior art BICMOS NAND gate 20. BICMOS NAND gate 20 includes a three input CMOS NAND gate 21, N-channel transistors 22-25, and NPN transistors 27 and 28. CMOS NAND gate 21 receives input logic signals labeled "A.sub.X ", "A.sub.Y ", and "A.sub.Z ", and provides an internal logic signal at a node labeled "N101". N-channel transistor 22 has a drain connected to a node labeled "N102", a gate connected to the output of CMOS NAND gate 21 at node N101, and a source connected to a negative power supply voltage terminal labeled "V.sub.SS ". NPN transistor 27 has a collector connected to a positive power supply voltage terminal labeled "V.sub.DD ", a base for receiving the internal logic signal from CMOS NAND gate 21 at node N101, and an emitter for providing an output signal labeled "V.sub.OUT ". N-channel transistor 23 has a drain connected to the emitter of transistor 27, a gate for receiving signal A.sub.X, and a source. N-channel transistor 24 has a drain connected to the source of transistor 23, a gate for receiving signal A.sub.Y, and a source. N-channel transistor 25 has a drain connected to the source of transistor 24, a gate for receiving signal A.sub.Z, and a source connected to the drain of transistor 22 at node N102. NPN transistor 28 has a collector connected to the emitter of transistor 27, a base connected to the source of transistor 25 at node N102, and an emitter connected to V.sub.SS.
BICMOS NAND gate 20 provides output signal V.sub.OUT as a logical NAND of input signals A.sub.X, A.sub.Y, and A.sub.Z at BICMOS levels. When at least one of signals A.sub.X, A.sub.Y, and A.sub.Z is a logic low input to CMOS NAND gate 21, output signal V.sub.OUT is a logic high. Only if all of input signals A.sub.X, A.sub.Y, and A.sub.Z are a logic high will V.sub.OUT be a logic low. The logic high voltage of output signal V.sub.OUT is equal to V.sub.DD, which is the logic high output of CMOS NAND gate 21, minus one base-emitter voltage drop (V.sub.BE) across bipolar transistor 27. The logic low voltage is approximately equal to a V.sub.BE above V.sub.SS. V.sub.DD is nominally 5.0 volts, and V.sub.SS is the system ground. But V.sub.DD may range from 3.0 volts to 7.0 volts depending on the application. Also, V.sub.DD may be the system ground and V.sub.SS equal to a negative power supply voltage. NPN transistor 27 is known in the art as a "pull-up" transistor, and NPN transistor 28 is known as a "pull-down" transistor.
For the case in which V.sub.DD is equal to 5.0 volts and CMOS NAND gate 21 applies a logic high of 5 volts to the base of bipolar transistor 27 at node N101, the V.sub.BE of transistor 27 of about 0.8 volts will cause output signal V.sub.OUT to be a logic high of approximately 4.2 volts. For the case in which CMOS NAND gate 21 provides a logic high output, at least one of transistors 23-25 will be non conductive, and transistor 22 will be conductive in response to the logic high at node N101, to discharge the base of transistor 28 and cause transistor 28 to be switched off.
For the case in which all of input signals A.sub.X, A.sub.Y, and A.sub.Z are a logic high, the output of CMOS NAND gate 21 at node N101 is a logic low. Transistor 27 is off (non conductive) and output signal V.sub.OUT is a logic low. All of series connected N-channel transistors 23-25 are conductive, thus clamping the base and collector of transistor 28 so that transistor 28 is base-emitter forward biased, causing output signal V.sub.OUT to be pulled to a logic low. Transistor 22 receives a logic low at its gate causing transistor 22 to be non conductive. The base-emitter voltage of transistor 28 is equal to approximately 0.8 volts and transistor 28 is conductive, until V.sub.OUT reaches about 0.8 volts. As V.sub.OUT drops further, node N102 will no longer be a V.sub.BE so that transistor 28 becomes non conductive. Thus, V.sub.OUT at a logic low is about a V.sub.BE above V.sub.SS.
A problem may occur with prior art BICMOS NAND gate 20 of FIG. 1 when operating at high frequency, or if the inputs become skewed, or glitched. The problem occurs when A.sub.Y and A.sub.Z are at a logic high and A.sub.X is a logic low and a sharp positive pulse appears at the gate of transistor 23. Because transistors 24 and 25 are already on (conductive), node N102 will be pulled high by the input glitch. The output of CMOS NAND gate 21 becomes a logic low making transistor 27 non conductive. Output signal V.sub.OUT will be pulled to a logic low because series connected transistors 23-25 cause transistors 28 to be switched on. As the sharp positive pulse, or glitch, falls, transistor 23 becomes non conductive and the output of CMOS NAND gate 21 becomes a logic high. However, the stored capacitance of transistors 24 and 25 prevents the voltage at node N102 from dropping, which causes transistor 28 to continue to conduct until the stored capacitance of transistors 24 and 25 has been exhausted. Transistor 28 may even be biased into saturation if output signal V.sub.OUT is pulled below the base voltage of transistor 28 before the stored charge on transistors 24 and 25 is depleted. If transistor 28 becomes saturated, large crowbar currents can result. This hinders output signal V.sub.OUT from transitioning back to a logic high state. Transistor 22 will eventually help to pull node N102 back down to V.sub.SS, but there is an undesirable delay because node N101 must also return to a logic high before transistor 22 can become conductive. The problem can occur whenever any two of transistors 23-25 are at a logic high and there is an input glitch on the third transistor. However, the problem is most severe when the input glitch occurs on transistor 23 because the stored charge of both transistors 24 and 25 is coupled to the base of transistor 28.
FIG. 2 illustrates in partial schematic form and partial logic diagram form a second prior art BICMOS NAND gate 30. In FIG. 2, the same reference numerals are assigned to corresponding elements of the circuit illustrated in FIG. 1. BICMOS NAND gate 30 includes N-channel transistor 26 to correct the problem caused by an input glitch, as addressed above with the prior art BICMOS NAND gate 20. N-channel transistor 26 has a drain connected to the base of transistor 28 at node N102, a gate connected to V.sub.DD, and a source connected to V.sub.SS.
Transistor 26 prevents transistor 28 from going into saturation when an input glitch occurs at the gate of transistor 23 by shunting the excess charge on the base of transistor 28 to V.sub.SS. This allows output signal V.sub.OUT to quickly return to a logic high after the input glitch subsides. The problem with transistor 28 being biased into saturation only occurs at high V.sub.DD, i.e. when V.sub.DD is greater than approximately 5 volts. Below approximately 5 volts, there is not enough current through the stack of series connected transistors 23-25 to bias transistor 28 into saturation. The problem with BICMOS NAND gate 30 is that at low V.sub.DD (below approximately 5 volts), transistor 26 conducts too much current, which impedes transistor 28 from becoming conductive. This hinders output signal V.sub.OUT from transitioning from a logic high to a logic low.